1. Field of the Invention
This disclosure relates to clock distribution mechanisms in integrated circuit devices and to clock generators using feedback for phase locking. A clock distribution mechanism according to one embodiment involves a clock generator having multiple feedback paths, one of which may include a delay locked loop.
2. Description of the Relevant Art
Recently, frequencies at which integrated circuit devices operate have rapidly increased as semiconductor fabrication processes have advanced. Advances in process technologies have resulted in devices that run at internal clock frequencies much higher than the external clock frequencies of the systems to which such devices are connected. However, if a high-speed device has a synchronous interface to an external system synchronization must be maintained between the external and internal clocks to maintain proper data sampling. To accomplish this and still maintain higher internal clock frequencies, phase locked loop technology has been integrated into such high speed devices. The phase locked loop allows a device to receive an external clock and generate an internal clock that is a multiple of the external clock while maintaining a close phase relationship between the external clock and the internal clock. For example a 33 MHz external clock may be multiplied in a phase locked loop to a 66 MHz internal clock. The phase locked loop keeps the 66 MHz internal clock in phase with the 33 MHz external clock so that every other edge of the 66 MHz internal clock will be approximately in synchronization with a corresponding clock edge of the 33 MHz external clock.
FIG. 1 illustrates a prior art clock generation technique for providing a high-speed internal clock 18 that maintains a phase relationship with an external clock 20. The technique of FIG. 1 includes a clock generator 12 that receives external clock 20 and generates a clock signal 16 that is a multiple of external clock 20. Clock signal 16 is fed back to clock generator 12 through feedback path 22. Clock generator 12 may include a phase locked loop that uses feedback clock 22 to maintain a phase lock between external clock 20 and feedback clock 22 so that clock signal 16 is generated substantially in phase with external clock 20. The typical phase locked loop contains a phase detector, an amplifier, and a voltage controlled oscillator. The phase detector compares external clock 20 to feedback clock 22 and generates an output that is a measure of their phase difference. The output measuring the phase error may be filtered and amplified and then used as input to the voltage controlled oscillator to adjust the generated clock signal according to the phase error. Thus, the voltage controlled oscillator will lock to the phase of the external clock maintaining a fixed phase relationship between the external clock and the feedback clock 22. Since clock signal 16 and feedback clock 22 are basically a common signal, the phase of clock signal 22 is also substantially locked to external clock 20. A counter device is connected to the output of the voltage control oscillator to generate clock signal 16 as a multiple of external clock 20.
Clock signal 16 is distributed throughout an integrated circuit device as the internal clock 18 by distribution path 14. Distribution path 14 may incorporate any conventional clock distribution scheme such as a buffered common node, a clock tree or a compressed tree. The larger and more complex the integrated circuit device is the more delay or skew will be introduced to the internal clock 18 by distribution path 14. As a result of this skew, internal clock 18 may become significantly out of phase with external clock 20. If the skew is too large, data errors may result. For example, the integrated circuit device will sample data from the external system based on internal clock 18. However, data may be valid in the external system according to external clock 20. If the skew or phase difference between internal clock 18 and external clock 20 is too large, data may be sampled by the integrated circuit during an invalid state.
FIG. 2 is an example of a prior art clock distribution technique that attempts to solve problems identified with the clock distribution technique of FIG. 1 above. The technique of FIG. 2 is similar to that of FIG. 1 except feedback clock 22 is taken from internal clock 18 instead of the generated clock signal 16. Clock generator 12 will maintain phase lock between feedback clock 22 and external clock 20. Since feedback clock 22 is taken from internal clock 18, a close phase relationship (i.e., "lock") is maintained between internal clock 18 and external clock 20. Therefore, data communications between the external system and the internal interface of the integrated circuit will be in closer synchronization than the technique of FIG. 1, resulting in more accurate data sampling at the I/O interface between the integrated circuit device and the external system.
As integrated circuit devices are operated at higher and higher frequencies they consume higher and higher amounts of power. Excess power consumption can result in heat related circuit errors. Furthermore, in hand held or portable systems reducing power consumption is important to maintain the battery life or operating duration of such systems. One accepted way to control power consumption in an integrated circuit device is to shut off the clock distribution to sections of the integrated circuit device that are not in use. However, for the clock distribution technique of FIG. 2, if the distribution path 14 is disabled then feedback clock 22 will also be disabled. Thus, phase lock will be lost and clock generator 12 will not be able to properly operate. Therefore, one disadvantage of the clock distribution technique of FIG. 2 is that internal clock 18 and distribution path 14 cannot be selectively or periodically disabled.
FIG. 3 is an example of a prior art distribution technique that attempts to solve the above identified problems of the clock distribution techniques of FIGS. 1 and 2. The clock distribution technique of FIG. 3 includes clock generator 12 that receives external clock 20 and generates clock signal 16 similar as in FIGS. 1 and 2. However, the technique of FIG. 3 separates the internal clock distribution into two distinct paths. I/O distribution path 24 provides I/O clock 28 which is used in the I/O interface between the integrated circuit device and the external system. Internal distribution path 26 is used to provide internal clock 18 to the core elements of the integrated circuit device. Feedback clock 22 is taken from I/O clock 28. Thus, clock generator 12 maintains a close phase relation between 10 clock 28 and external clock 20. Therefore, data communications between the I/O buffers of the integrated circuit and the external system are reliably performed. Also, the technique of FIG. 3 provides disable signal 30 for disabling internal distribution path 26 and thus internal clock 18. Internal clock 18 may thus be disabled while maintaining phase lock in the clock generator 12. However, the technique of FIG. 3 has a drawback in that internal clock 18 is not closely phase matched to I/O clock 28 and external clock 20. To overcome this problem double buffering may be used in the I/O interface to synchronize data to the internal clock 18. However, double buffering may require a large amount of additional die area and thus be prohibitive in regard to cost and area. Double buffering also requires an additional clock cycle to propagate data into the device. This delay may cause architectural problems in devices such as microprocessors.
FIG. 4 is an example of another prior art technique that attempts to maintain a close phase relationship between the internal and external clocks and also allow the internal clock to be disabled without losing phase lock. The technique of FIG. 4 includes clock generator 12 that generates clock signal 16 as a multiple of external clock 20. Clock signal 16 is distributed throughout the integrated circuit device as internal clock 18 by distribution path 24. Internal clock 18 is used for both core elements and the I/O interface. Clock signal 16 is also routed through matching path 32 to provide feedback clock 22 to the clock generator 12 for maintaining phase lock between feedback clock 22 and external clock 20. Matching path 32 is designed to approximate the delay through distribution path 34. Thus, if the delay from clock signal 16 to feedback clock 22 closely matches the delay from clock signal 16 to internal clock 18 then the phase lock between feedback clock 22 and external clock 20 will also provide a close phase relationship between internal clock 18 and external clock 20. Therefore, the I/O interface of the integrated circuit device will provide accurate data sampling of the external system and double buffering will not be required to synchronize to the core elements.
Furthermore, disable signal 30 is provided to disable internal clock 18 and distribution path 34. Internal clock 18 may be disabled by asserting disable signal 30. However, phase lock is not lost when internal clock 18 is disabled because matching path 32 continues to provide feedback clock 22 to clock generator 12. When disable signal 30 is unasserted a close phase relationship is immediately restored between internal clock 18 and external clock 20. Matching path 32 may be created by routing conductive trace and/or using delay elements to approximate the delay of distribution path 34. However, since matching path 32 is not the actual distribution path for the internal clock, it is very difficult to create an exact delay match. Furthermore, if matching path 32 is created in one localized area of the integrated circuit device it will not approximate process variations across the integrated circuit device. For example, distribution path 34 distributes internal clock 18 across the entire integrated circuit device and thus takes into account variations in line width and other spacings inherent to the fabrication process used to create the integrated circuit device. These process variations cannot be accounted for in a localized matching path. If the integrated circuit device operates at an internal clock frequency of 500 MHz for example, the difference in delay between matching path 32 and distribution path 34 can be significant. In such an example a 200 pico-second difference in delay between matching path 32 and distribution path 34 results in a 10% clock period skew of internal clock 18. Such a skew error may be intolerable in a high frequency design, especially when clock jitter and phase error are also taken into account.
A need therefore exists for a clock distribution technique that overcomes the problems identified in the techniques of FIGS. 1 through 4 above. Thus, it is desirable to have a clock distribution technique that maintains a close phase relation between the internal clock and the external clock at both the core elements and the I/O interface. Furthermore, it is desirable to avoid double buffering at the I/O interface. It is yet further desirable to be able to disable the internal clock without losing phase lock in the clock generator. Finally, it is desirable for the phase relationship between the internal clock and the external clock to be extremely close so that as much of the internal clock period as possible is available in the integrated circuit device for high frequency applications.